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A mixed-signal structured AdEx neuron for accelerated neuromorphic cores

Here, we describe a multicompartment neuron circuit based on the adaptive-exponential I&F (AdEx) model, developed for the second-generation BrainScaleS hardware. Based on an existing modular leaky integrate-and-fire (LIF) architecture designed in 65-nm CMOS, the circuit features exponential spik...

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Hauptverfasser: Aamir, Syed Ahmed (VerfasserIn) , Müller, Paul (VerfasserIn) , Kiene, Gerd (VerfasserIn) , Kriener, Laura (VerfasserIn) , Stradmann, Yannik (VerfasserIn) , Grübl, Andreas (VerfasserIn) , Schemmel, Johannes (VerfasserIn) , Meier, Karlheinz (VerfasserIn)
Dokumenttyp: Article (Journal)
Sprache:Englisch
Veröffentlicht: July 24, 2018
In: IEEE transactions on biomedical circuits and systems
Year: 2018, Jahrgang: 12, Heft: 5, Pages: 1027-1037
ISSN:1940-9990
DOI:10.1109/TBCAS.2018.2848203
Online-Zugang:Verlag, kostenfrei, Volltext: https://dx.doi.org/10.1109/TBCAS.2018.2848203
Verlag, kostenfrei, Volltext: https://ieeexplore.ieee.org/document/8419063
Volltext
Verfasserangaben:Syed Ahmed Aamir, student member, IEEE, Paul Müller, Gerd Kiene, Laura Kriener, Yannik Stradmann, Andreas Grübl, Johannes Schemmel, member, IEEE, and Karlheinz Meier, member, IEEE

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520 |a Here, we describe a multicompartment neuron circuit based on the adaptive-exponential I&F (AdEx) model, developed for the second-generation BrainScaleS hardware. Based on an existing modular leaky integrate-and-fire (LIF) architecture designed in 65-nm CMOS, the circuit features exponential spike generation, neuronal adaptation, intercompartmental connections as well as a conductance-based reset. The design reproduces a diverse set of firing patterns observed in cortical pyramidal neurons. Further, it enables the emulation of sodium and calcium spikes, as well as N-methyl-D-aspartate plateau potentials known from apical and thin dendrites. We characterize the AdEx circuit extensions and exemplify how the interplay between passive and nonlinear active signal processing enhances the computational capabilities of single (but structured) on-chip neurons. 
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