Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a R...

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Hauptverfasser: Balbi, Gabriele (VerfasserIn) , Bindi, M. (VerfasserIn) , Falchieri, D. (VerfasserIn) , Furini, M. (VerfasserIn) , Gabrielli, A. (VerfasserIn) , Kugel, Andreas (VerfasserIn) , Travaglini, R. (VerfasserIn) , Wensing, M. (VerfasserIn)
Dokumenttyp: Article (Journal) Konferenzschrift
Sprache:Englisch
Veröffentlicht: January 8, 2013
In: Journal of Instrumentation
Year: 2013, Jahrgang: 8
ISSN:1748-0221
DOI:10.1088/1748-0221/8/01/C01012
Online-Zugang:Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1088/1748-0221/8/01/C01012
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Verfasserangaben:G. Balbi, M. Bindi, D. Falchieri, M. Furini, A. Gabrielli, A. Kugel, R. Travaglini and M. Wensing

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520 |a The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported. 
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