Concepts for the XIDer readout ASIC incorporating a pipelined ADC with very low dead time

We present the first concept for the analog front-end of the readout ASIC for the XIDer (X-ray Integrating Detector) detector system which is being developed by a collaboration between the ESRF and Heidelberg University. The ESRF's Extremely Brilliant Source (EBS) upgrade which has been complet...

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Hauptverfasser: Schimansky, David (VerfasserIn) , Busca, P. (VerfasserIn) , Erdinger, Florian (VerfasserIn) , Fajardo, P. (VerfasserIn) , Fischer, Peter (VerfasserIn)
Dokumenttyp: Article (Journal)
Sprache:Englisch
Veröffentlicht: 15 March 2021
In: Journal of Instrumentation
Year: 2021, Jahrgang: 16, Heft: 3, Pages: 1-12
ISSN:1748-0221
DOI:10.1088/1748-0221/16/03/P03023
Online-Zugang:Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1088/1748-0221/16/03/P03023
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Verfasserangaben:D. Schimansky, P. Busca, F. Erdinger, P. Fajardo and P. Fischer

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520 |a We present the first concept for the analog front-end of the readout ASIC for the XIDer (X-ray Integrating Detector) detector system which is being developed by a collaboration between the ESRF and Heidelberg University. The ESRF's Extremely Brilliant Source (EBS) upgrade which has been completed recently provides X-ray beams of unprecedented quality, requiring new photon detection instruments. The XIDer project has been launched to develop a new versatile pixel detector which will be tailored to match requirements imposed by this upgrade. The core challenges include fast signal acquisition, large dynamic range and single photon sensitivity. A first prototype ASIC for the analog front-end of a single pixel has been manufactured. It is based on a pipelined two-stage charge removal circuit which digitizes the incident signal on the fly. We will present measurement results of the first test chip and concepts for the final system-on-chip implementation integrating several tens of thousands of pixels. 
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