A 256 channel 8-Bit current digitizer ASIC for the Belle-II PXD
The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode�...
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| Main Authors: | , , , |
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| Format: | Article (Journal) Conference Paper |
| Language: | English |
| Published: |
January 17, 2011
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| In: |
Journal of Instrumentation
Year: 2011, Volume: 6, Issue: 1, Pages: 1-6 |
| ISSN: | 1748-0221 |
| DOI: | 10.1088/1748-0221/6/01/C01085 |
| Online Access: | Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1088/1748-0221/6/01/C01085
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| Author Notes: | J. Knopf, P. Fischer, C. Kreidl and I. Peric |
MARC
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| 520 | |a The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of < 100 ns. One of the major parts in the front-end electronics chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible. A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose. Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern. The chip was realized on a 3.2mm × 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module. Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented. | ||
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