A compact front-end circuit for a monolithic sensor in a 65-nm CMOS imaging technology - Piro, Francesco; Rinella, G. Aglieri; Andronic, A.; Antonelli, M.; Aresti, M.; Baccomi, R.; Becht, Pascal; Beolè, S.; Braach, J.; Buckland, M. D.; Buschmann, E.; Camerini, P.; et al. (IEEE transactions on nuclear science, 2023)
This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5×1.5 mm including a matrix of 32×32 pixels with a pitch of 15 μ \textm . The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42 μ \textm^2 and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design.
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