Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process - Aglieri Rinella, Gianluca; Aglietta, Luca; Antonelli, Matias; Barile, Francesco; Benotto, Franco; Beolè, Stefania Maria; Botta, Elena; Bruno, Giuseppe Eugenio; Carnesecchi, Francesca; Colella, Domenico; Colelli, Angelo; Contin, Giacomo; et al. (Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2024)
In the context of the CERN EP R&D on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65nm process has been qualified for use in high energy physics, and adopted for the ALICE ITS3 upgrade. An Analog Pixel Test Structure (APTS) featuring fast per pixel operational-amplifier-based buffering for a small matrix of four by four pixels, with a sensor with a small collection electrode and a very non-uniform electric field, was designed to allow detailed characterization of the pixel performance in this technology. Several variants of this chip with different pixel designs have been characterized with a 120GeV/c positive hadron beam. This result indicates that the APTS-OA prototype variants with the best performance achieve a time resolution of 63ps with a detection efficiency exceeding 99% and a spatial resolution of 2μm, highlighting the potential of TPSCo 65 nm CMOS imaging technology for high-energy physics and other fields requiring precise time measurement, high detection efficiency, and excellent spatial resolution.