Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC
by Camplani, A. (Author)
, Dittmeier, Sebastian (Author)
, Annovi, A. (Author)
, Axiotis, K. (Author)
, Beccherle, R. (Author)
, Biesuz, N. (Author)
, Brenner, R. (Author)
, Debieux, S. (Author)
, Ellert, M. (Author)
, Francavilla, P. (Author)
, Giannetti, P. (Author)
, Kordas, K. (Author)
, Martensson, M. (Author)
, Mastrandrea, P. (Author)
, Noulas, C. (Author)
, Oechsle, J. (Author)
, Piendibene, M. (Author)
, Poggi, R. (Author)
, Schöning, André (Author)
, Sfyrla, A. (Author)
, Sotiropoulou, C. L. (Author)
, Steentoft, J. (Author)
, Tsiakiris, T. (Author)
, Xella, S. (Author)
, Zinßer, Joachim (Author)
,
Call Number:
Loading…
Located:
Loading…
Article (Journal)
Online Resource