An accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture
We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype high input count analog neural network with digital...
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| Hauptverfasser: | , , , , , , , |
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| Dokumenttyp: | Article (Journal) |
| Sprache: | Englisch |
| Veröffentlicht: |
27 June 2018
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| In: |
IEEE transactions on biomedical circuits and systems
Year: 2018, Jahrgang: 65, Heft: 12, Pages: 4299-4312 |
| ISSN: | 1940-9990 |
| DOI: | 10.1109/TCSI.2018.2840718 |
| Online-Zugang: | Verlag, Volltext: https://doi.org/10.1109/TCSI.2018.2840718
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| Verfasserangaben: | Syed Ahmed Aamir, student member, IEEE, Yannik Stradmann, Paul Müller, Christian Pehle, Andreas Hartel, Andreas Grübl, Johannes Schemmel, member, IEEE, and Karlheinz Meier, member, IEEE |
MARC
| LEADER | 00000caa a2200000 c 4500 | ||
|---|---|---|---|
| 001 | 1662699956 | ||
| 003 | DE-627 | ||
| 005 | 20220816124345.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 190402s2018 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1109/TCSI.2018.2840718 |2 doi | |
| 035 | |a (DE-627)1662699956 | ||
| 035 | |a (DE-599)KXP1662699956 | ||
| 035 | |a (OCoLC)1341205879 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rda | ||
| 041 | |a eng | ||
| 084 | |a 29 |2 sdnb | ||
| 100 | 1 | |a Aamir, Syed Ahmed |e VerfasserIn |0 (DE-588)1181379075 |0 (DE-627)1662668317 |4 aut | |
| 245 | 1 | 3 | |a An accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture |c Syed Ahmed Aamir, student member, IEEE, Yannik Stradmann, Paul Müller, Christian Pehle, Andreas Hartel, Andreas Grübl, Johannes Schemmel, member, IEEE, and Karlheinz Meier, member, IEEE |
| 264 | 1 | |c 27 June 2018 | |
| 300 | |a 14 | ||
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 500 | |a Gesehen am 02.04.2019 | ||
| 520 | |a We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype high input count analog neural network with digital learning system chip. Designed as continuous-time circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration, and measurement results from individual sub-circuits across multiple dies. The circuit dynamics matches with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing. | ||
| 650 | 4 | |a 65nm CMOS | |
| 650 | 4 | |a accelerated dynamics | |
| 650 | 4 | |a accelerated LIF neuronal network array | |
| 650 | 4 | |a Analog integrated circuits | |
| 650 | 4 | |a analog network core | |
| 650 | 4 | |a Biological system modeling | |
| 650 | 4 | |a circuit design | |
| 650 | 4 | |a circuit dynamics | |
| 650 | 4 | |a CMOS integrated circuits | |
| 650 | 4 | |a Computational modeling | |
| 650 | 4 | |a Computer architecture | |
| 650 | 4 | |a continuous-time circuits | |
| 650 | 4 | |a cortical processing | |
| 650 | 4 | |a design methodology | |
| 650 | 4 | |a digital learning system chip | |
| 650 | 4 | |a digital spike event output | |
| 650 | 4 | |a high input count analog neural network | |
| 650 | 4 | |a input current | |
| 650 | 4 | |a integrated circuit design | |
| 650 | 4 | |a Integrated circuit modeling | |
| 650 | 4 | |a integrated circuit modelling | |
| 650 | 4 | |a leaky integrate and fire | |
| 650 | 4 | |a leaky integrate-and-fire neuron circuit design | |
| 650 | 4 | |a LIF mathematical model | |
| 650 | 4 | |a membrane time constants | |
| 650 | 4 | |a mixed analogue-digital integrated circuits | |
| 650 | 4 | |a mixed-signal neuromorphic architecture | |
| 650 | 4 | |a multiple dies | |
| 650 | 4 | |a neural chips | |
| 650 | 4 | |a neural net architecture | |
| 650 | 4 | |a neuromorphic | |
| 650 | 4 | |a Neuromorphics | |
| 650 | 4 | |a neuronal array | |
| 650 | 4 | |a Neurons | |
| 650 | 4 | |a opamp | |
| 650 | 4 | |a OTA | |
| 650 | 4 | |a prototype chip | |
| 650 | 4 | |a prototype high input count analog neural network | |
| 650 | 4 | |a refractory periods | |
| 650 | 4 | |a second-generation BrainScaleS mixed-signal CMOS neuromorphic hardware | |
| 650 | 4 | |a size 65 nm | |
| 650 | 4 | |a spiking neuron | |
| 650 | 4 | |a Synapses | |
| 650 | 4 | |a tunable resistor | |
| 650 | 4 | |a winner-take-all network | |
| 700 | 1 | |a Stradmann, Yannik |e VerfasserIn |0 (DE-588)1181379393 |0 (DE-627)1662664249 |4 aut | |
| 700 | 1 | |a Müller, Paul |e VerfasserIn |0 (DE-588)1147992304 |0 (DE-627)1007481080 |0 (DE-576)496128736 |4 aut | |
| 700 | 1 | |a Pehle, Christian |d 1988- |e VerfasserIn |0 (DE-588)1093238550 |0 (DE-627)853202338 |0 (DE-576)46265527X |4 aut | |
| 700 | 1 | |a Hartel, Andreas |e VerfasserIn |0 (DE-588)142039268 |0 (DE-627)704126397 |0 (DE-576)326738770 |4 aut | |
| 700 | 1 | |a Grübl, Andreas |e VerfasserIn |0 (DE-588)133198456 |0 (DE-627)538271450 |0 (DE-576)299688208 |4 aut | |
| 700 | 1 | |a Schemmel, Johannes |e VerfasserIn |0 (DE-588)1025834607 |0 (DE-627)72488291X |0 (DE-576)370821440 |4 aut | |
| 700 | 1 | |a Meier, Karlheinz |d 1955-2018 |e VerfasserIn |0 (DE-588)1025835115 |0 (DE-627)724884114 |0 (DE-576)370822269 |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |a Institute of Electrical and Electronics Engineers |t IEEE transactions on biomedical circuits and systems |d New York, NY : IEEE, 2007 |g 65(2018), 12, Seite 4299-4312 |h Online-Ressource |w (DE-627)521455588 |w (DE-600)2260089-9 |w (DE-576)263594009 |x 1940-9990 |7 nnas |
| 773 | 1 | 8 | |g volume:65 |g year:2018 |g number:12 |g pages:4299-4312 |g extent:14 |a An accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture |
| 856 | 4 | 0 | |u https://doi.org/10.1109/TCSI.2018.2840718 |x Verlag |x Resolving-System |3 Volltext |
| 951 | |a AR | ||
| 992 | |a 20190402 | ||
| 993 | |a Article | ||
| 994 | |a 2018 | ||
| 998 | |g 1025835115 |a Meier, Karlheinz |m 1025835115:Meier, Karlheinz |d 130000 |d 130700 |e 130000PM1025835115 |e 130700PM1025835115 |k 0/130000/ |k 1/130000/130700/ |p 8 |y j | ||
| 998 | |g 1025834607 |a Schemmel, Johannes |m 1025834607:Schemmel, Johannes |d 130000 |d 130700 |e 130000PS1025834607 |e 130700PS1025834607 |k 0/130000/ |k 1/130000/130700/ |p 7 | ||
| 998 | |g 133198456 |a Grübl, Andreas |m 133198456:Grübl, Andreas |d 130000 |d 130700 |e 130000PG133198456 |e 130700PG133198456 |k 0/130000/ |k 1/130000/130700/ |p 6 | ||
| 998 | |g 142039268 |a Hartel, Andreas |m 142039268:Hartel, Andreas |d 130000 |d 130700 |e 130000PH142039268 |e 130700PH142039268 |k 0/130000/ |k 1/130000/130700/ |p 5 | ||
| 998 | |g 1093238550 |a Pehle, Christian |m 1093238550:Pehle, Christian |d 130000 |d 130700 |e 130000PP1093238550 |e 130700PP1093238550 |k 0/130000/ |k 1/130000/130700/ |p 4 | ||
| 998 | |g 1147992304 |a Müller, Paul |m 1147992304:Müller, Paul |d 130000 |d 130700 |e 130000PM1147992304 |e 130700PM1147992304 |k 0/130000/ |k 1/130000/130700/ |p 3 | ||
| 998 | |g 1181379393 |a Stradmann, Yannik |m 1181379393:Stradmann, Yannik |d 130000 |d 130700 |e 130000PS1181379393 |e 130700PS1181379393 |k 0/130000/ |k 1/130000/130700/ |p 2 | ||
| 998 | |g 1181379075 |a Aamir, Syed Ahmed |m 1181379075:Aamir, Syed Ahmed |d 130000 |d 130700 |e 130000PA1181379075 |e 130700PA1181379075 |k 0/130000/ |k 1/130000/130700/ |p 1 |x j | ||
| 999 | |a KXP-PPN1662699956 |e 3417696801 | ||
| BIB | |a Y | ||
| SER | |a journal | ||
| JSO | |a {"physDesc":[{"extent":"14 S."}],"name":{"displayForm":["Syed Ahmed Aamir, student member, IEEE, Yannik Stradmann, Paul Müller, Christian Pehle, Andreas Hartel, Andreas Grübl, Johannes Schemmel, member, IEEE, and Karlheinz Meier, member, IEEE"]},"person":[{"display":"Aamir, Syed Ahmed","given":"Syed Ahmed","family":"Aamir","role":"aut","roleDisplay":"VerfasserIn"},{"role":"aut","roleDisplay":"VerfasserIn","family":"Stradmann","given":"Yannik","display":"Stradmann, Yannik"},{"role":"aut","roleDisplay":"VerfasserIn","given":"Paul","family":"Müller","display":"Müller, Paul"},{"family":"Pehle","given":"Christian","display":"Pehle, Christian","role":"aut","roleDisplay":"VerfasserIn"},{"roleDisplay":"VerfasserIn","role":"aut","given":"Andreas","family":"Hartel","display":"Hartel, Andreas"},{"display":"Grübl, Andreas","given":"Andreas","family":"Grübl","roleDisplay":"VerfasserIn","role":"aut"},{"given":"Johannes","family":"Schemmel","display":"Schemmel, Johannes","roleDisplay":"VerfasserIn","role":"aut"},{"role":"aut","roleDisplay":"VerfasserIn","given":"Karlheinz","family":"Meier","display":"Meier, Karlheinz"}],"language":["eng"],"title":[{"title":"An accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture","title_sort":"accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture"}],"recId":"1662699956","note":["Gesehen am 02.04.2019"],"origin":[{"dateIssuedKey":"2018","dateIssuedDisp":"27 June 2018"}],"relHost":[{"disp":"Institute of Electrical and Electronics EngineersIEEE transactions on biomedical circuits and systems","titleAlt":[{"title":"Transactions on biomedical circuits and systems"}],"physDesc":[{"extent":"Online-Ressource"}],"title":[{"title":"IEEE transactions on biomedical circuits and systems","title_sort":"IEEE transactions on biomedical circuits and systems"}],"language":["eng"],"note":["Gesehen am 01.10.15"],"corporate":[{"display":"Institute of Electrical and Electronics Engineers","roleDisplay":"VerfasserIn","role":"aut"}],"recId":"521455588","type":{"bibl":"periodical","media":"Online-Ressource"},"origin":[{"publisher":"IEEE","publisherPlace":"New York, NY","dateIssuedKey":"2007","dateIssuedDisp":"2007-"}],"id":{"zdb":["2260089-9"],"eki":["521455588"],"issn":["1940-9990"]},"pubHistory":["1.2007 -"],"part":{"issue":"12","text":"65(2018), 12, Seite 4299-4312","volume":"65","extent":"14","year":"2018","pages":"4299-4312"}}],"type":{"bibl":"article-journal","media":"Online-Ressource"},"id":{"eki":["1662699956"],"doi":["10.1109/TCSI.2018.2840718"]}} | ||
| SRT | |a AAMIRSYEDAACCELERATE2720 | ||