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An accelerated LIF neuronal network array for a large-scale mixed-signal neuromorphic architecture

We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype high input count analog neural network with digital...

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Hauptverfasser: Aamir, Syed Ahmed (VerfasserIn) , Stradmann, Yannik (VerfasserIn) , Müller, Paul (VerfasserIn) , Pehle, Christian (VerfasserIn) , Hartel, Andreas (VerfasserIn) , Grübl, Andreas (VerfasserIn) , Schemmel, Johannes (VerfasserIn) , Meier, Karlheinz (VerfasserIn)
Dokumenttyp: Article (Journal)
Sprache:Englisch
Veröffentlicht: 27 June 2018
In: IEEE transactions on biomedical circuits and systems
Year: 2018, Jahrgang: 65, Heft: 12, Pages: 4299-4312
ISSN:1940-9990
DOI:10.1109/TCSI.2018.2840718
Online-Zugang:Verlag, Volltext: https://doi.org/10.1109/TCSI.2018.2840718
Volltext
Verfasserangaben:Syed Ahmed Aamir, student member, IEEE, Yannik Stradmann, Paul Müller, Christian Pehle, Andreas Hartel, Andreas Grübl, Johannes Schemmel, member, IEEE, and Karlheinz Meier, member, IEEE
Beschreibung
Zusammenfassung:We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaled-down prototype high input count analog neural network with digital learning system chip. Designed as continuous-time circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration, and measurement results from individual sub-circuits across multiple dies. The circuit dynamics matches with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing.
Beschreibung:Gesehen am 02.04.2019
Beschreibung:Online Resource
ISSN:1940-9990
DOI:10.1109/TCSI.2018.2840718

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