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PACIFIC: SiPM readout ASIC for LHCb upgrade

A new 64-channel mixed-signal ASIC is presented: PACIFIC. It was developed in TSMC 130 nm CMOS technology for the readout of the Scintillating Fibre Tracker, as a part of the LHCb upgrade. This detector is based on 250 μ m scintillating fibers readout by custom designed 128-channel silicon photomult...

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Main Authors: Mazorra de Cos, José (Author) , Chanal, Hervé (Author) , Comerma-Montells, Albert (Author) , Gascón Fora, David (Author) , Gómez Fernández, Sergio (Author) , Han, Xiaoxue (Author) , Pillet, Nicolas (Author) , Vandaelle, Richard (Author)
Format: Article (Journal)
Language:English
Published: 2018
In: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment
Year: 2017, Volume: 912, Pages: 354-358
ISSN:1872-9576
DOI:10.1016/j.nima.2017.12.044
Online Access:Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1016/j.nima.2017.12.044
Verlag, lizenzpflichtig, Volltext: http://www.sciencedirect.com/science/article/pii/S0168900217314377
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Author Notes:José Mazorra de Cos, Hervé Chanal, Albert Comerma Montells, David Gascón Fora, Sergio Gómez Fernández, Xiaoxue Han, Nicolas Pillet, Richard Vandaelle, on behalf of the LHCb Scintillating Fibre Tracker Group
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Summary:A new 64-channel mixed-signal ASIC is presented: PACIFIC. It was developed in TSMC 130 nm CMOS technology for the readout of the Scintillating Fibre Tracker, as a part of the LHCb upgrade. This detector is based on 250 μ m scintillating fibers readout by custom designed 128-channel silicon photomultiplier arrays. It will cover a total area of 340 m2, distributed over the 12 planes that compose it. The sensors are connected directly to PACIFIC without any interface components. The ASIC acquires the current pulses using a current conveyor. A fast double pole-zero cancellation shaper is used to minimize spillover. The charge is then collected using gated integrators, with a twofold interleaved scheme to minimize dead time. The resulting voltage level is digitized with a configurable 2 bit non-linear flash ADC. The output is a 320 Mbps differential signal produced by the serializers, which gather the results from four adjacent channels.
Item Description:Available online 21 December 2017
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Physical Description:Online Resource
ISSN:1872-9576
DOI:10.1016/j.nima.2017.12.044

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