PADI, an ultrafast preamplifier: discriminator ASIC for time-of-flight measurements
The design of a general-purpose PreAmplifier-DIscriminator ASIC chip, PADI, is presented in this article. PADI is intended to be used as Front-End-Electronics (FEE) for reading out the timing Resistive-Plate Chambers (RPCs) in the time-of-flight (ToF) wall of the CBM detector for the future FAIR fac...
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| Main Authors: | , , , , , , , , , , , |
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| Format: | Article (Journal) |
| Language: | English |
| Published: |
10 April 2014
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| In: |
IEEE transactions on nuclear science
Year: 2014, Volume: 61, Issue: 2, Pages: 1015-1023 |
| ISSN: | 1558-1578 |
| DOI: | 10.1109/TNS.2014.2305999 |
| Online Access: | Resolving-System, lizenzpflichtig, Volltext: https://doi.org/10.1109/TNS.2014.2305999 Verlag, lizenzpflichtig, Volltext: https://ieeexplore.ieee.org/document/6786378/authors 
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| Author Notes: | M. Ciobanu, N. Herrmann, K.D. Hildenbrand, M. Kiš, A. Schüttauf, H. Flemming, H. Deppe, S. Löchner, J. Frühauf, I. Deppner, P.A. Loizeau, and M. Träger |
| Summary: | The design of a general-purpose PreAmplifier-DIscriminator ASIC chip, PADI, is presented in this article. PADI is intended to be used as Front-End-Electronics (FEE) for reading out the timing Resistive-Plate Chambers (RPCs) in the time-of-flight (ToF) wall of the CBM detector for the future FAIR facility in Darmstadt-Germany, which will comprise about 100,000 channels in a 150 m2 area. The evolution of this 0.18 μm CMOS technology design will be presented, from the first prototype PADI-1 to the last one, PADI-8, as well as its features and test results. |
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| Item Description: | Gesehen am 16.09.2020 |
| Physical Description: | Online Resource |
| ISSN: | 1558-1578 |
| DOI: | 10.1109/TNS.2014.2305999 |