Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card
The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a R...
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| Auteurs principaux: | , , , , , , , |
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| Format: | Article (Journal) Conference Paper |
| Langue: | anglais |
| Publié: |
January 8, 2013
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| In: |
Journal of Instrumentation
Year: 2013, Volume: 8 |
| ISSN: | 1748-0221 |
| DOI: | 10.1088/1748-0221/8/01/C01012 |
| Accès en ligne: | Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1088/1748-0221/8/01/C01012
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| Notes sur l'auteur: | G. Balbi, M. Bindi, D. Falchieri, M. Furini, A. Gabrielli, A. Kugel, R. Travaglini and M. Wensing |
| Résumé: | The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported. |
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| Description: | Gesehen am 12.11.2020 Topical workshop on electronics for particle physics 2012, 17-21 September 2012, Oxford, U.K |
| Description matérielle: | Online Resource |
| ISSN: | 1748-0221 |
| DOI: | 10.1088/1748-0221/8/01/C01012 |