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Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a R...

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Bibliographic Details
Main Authors: Balbi, Gabriele (Author) , Bindi, M. (Author) , Falchieri, D. (Author) , Furini, M. (Author) , Gabrielli, A. (Author) , Kugel, Andreas (Author) , Travaglini, R. (Author) , Wensing, M. (Author)
Format: Article (Journal) Conference Paper
Language:English
Published: January 8, 2013
In: Journal of Instrumentation
Year: 2013, Volume: 8
ISSN:1748-0221
DOI:10.1088/1748-0221/8/01/C01012
Online Access:Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1088/1748-0221/8/01/C01012
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Author Notes:G. Balbi, M. Bindi, D. Falchieri, M. Furini, A. Gabrielli, A. Kugel, R. Travaglini and M. Wensing
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Summary:The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.
Item Description:Gesehen am 12.11.2020
Topical workshop on electronics for particle physics 2012, 17-21 September 2012, Oxford, U.K
Physical Description:Online Resource
ISSN:1748-0221
DOI:10.1088/1748-0221/8/01/C01012

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