High-speed and low-cost in-array memristive multipliers using SIXOR and TMSL logics
Memristive systems have many promising features, making them suitable for both storage and computation. Memristors can perform logical operations and they can be used as the basic structures in digital circuits such as adders and multipliers. In this paper, at first, a new fast and low-cost Full-Add...
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| Main Authors: | , , |
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| Format: | Article (Journal) |
| Language: | English |
| Published: |
2026
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| In: |
IEEE transactions on nanotechnology
Year: 2026, Volume: 25, Pages: 13-25 |
| ISSN: | 1941-0085 |
| DOI: | 10.1109/TNANO.2025.3566272 |
| Online Access: | Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1109/TNANO.2025.3566272 Verlag, lizenzpflichtig, Volltext: https://ieeexplore.ieee.org/document/10981683 
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| Author Notes: | Roya Rahimi Disfani, Mojtaba Valinataj, and Nima TaheriNejad, member, IEEE |
| Summary: | Memristive systems have many promising features, making them suitable for both storage and computation. Memristors can perform logical operations and they can be used as the basic structures in digital circuits such as adders and multipliers. In this paper, at first, a new fast and low-cost Full-Adder (FA) is proposed using Single-cycle In-memristor XOR (SIXOR) and Three Memristors Stateful Logic (TMSL) gates that benefits from the advantages of both logics. Then, the proposed FA is used as one of the basic units inside two new array multipliers. The first proposed multiplier is designed in such a way that it has the lowest computational steps (delay) among the existing designs. This design has on average around 70% lower delay compared to the existing designs. The second proposed multiplier, as the low-cost design, requires a very low number of memristors thanks to reusing the existing resources more efficiently, while still having a low delay. This multiplier achieves on average around 36% memristor reduction compared to the state-of-the-art multipliers. Based on the analysis, both proposed array multipliers have notable efficiency advantages compared to the state-of-the-art designs based on different Figures of Merit (FoMs). For example, based on the balanced Figure of Merit (FoM), in which the number of computational steps and the number of required memristors have equal weight, the first and the second proposed multipliers achieve up to 4.6× and 14.9× improvements, respectively, compared to the existing designs in 64-bit multiplication. |
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| Item Description: | Gesehen am 13.03.2026 |
| Physical Description: | Online Resource |
| ISSN: | 1941-0085 |
| DOI: | 10.1109/TNANO.2025.3566272 |