Low power Analog Digital Converter for a silicon photomultiplier readout ASIC
We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end “KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the...
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| Main Authors: | , , , |
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| Format: | Article (Journal) |
| Language: | English |
| Published: |
30 April 2015
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| In: |
Journal of Instrumentation
Year: 2015, Volume: 10, Issue: 04 |
| ISSN: | 1748-0221 |
| DOI: | 10.1088/1748-0221/10/04/C04041 |
| Online Access: | Verlag, lizenzpflichtig, Volltext: https://doi.org/10.1088/1748-0221/10/04/C04041
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| Author Notes: | K. Briggl, H. Chen, W. Shen and H.C. Schultz-Coulon |
| Summary: | We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end “KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit. |
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| Item Description: | Gesehen am 28.05.2020 |
| Physical Description: | Online Resource |
| ISSN: | 1748-0221 |
| DOI: | 10.1088/1748-0221/10/04/C04041 |