A compact front-end circuit for a monolithic sensor in a 65-nm CMOS imaging technology
This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5\times1.5 mm includin...
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| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
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| Format: | Article (Journal) |
| Language: | English |
| Published: |
27 July 2023
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| In: |
IEEE transactions on nuclear science
Year: 2023, Volume: 70, Issue: 9, Pages: 2191-2200 |
| ISSN: | 1558-1578 |
| DOI: | 10.1109/TNS.2023.3299333 |
| Online Access: | Verlag, kostenfrei, Volltext: https://doi.org/10.1109/TNS.2023.3299333 Verlag, kostenfrei, Volltext: https://ieeexplore.ieee.org/document/10196055 |
| Author Notes: | F. Piro, Graduate Student Member, IEEE, G. Aglieri Rinella, A. Andronic, M. Antonelli, M. Aresti, R. Baccomi, P. Becht, S. Beolè, J. Braach, M.D. Buckland, E. Buschmann, P. Camerini, F. Carnesecchi, L. Cecconi, E. Charbon, Fellow, IEEE, G. Contin, D. Dannheim, J. de Melo, W. Deng, A. di Mauro, M. Dimitrova Vassilev, S. Emiliani, J. Hasenbichler, H. Hillemanns, Senior Member, IEEE, G.H. Hong, A. Isakov, A. Junique, A. Kluge, A. Kotliarov, F. Křížek, T. Kugathasan, L. Lautner, C. Lemoine, M. Mager, D. Marras, P. Martinengo, S. Masciocchi, M.W. Menzel, M. Munker, A. Rachevski, K. Rebane, F. Reidt, R. Russo, I. Sanna, V. Sarritzu, S. Senyukov, W. Snoeys, Senior Member, IEEE, J. Sonneveld, M. Šuljić, P. Svihra, N. Tiltmann, G. Usai, J.B. van Beelen, C. Vernieri, A. Villani |
| Summary: | This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5\times1.5 mm including a matrix of 32\times32 pixels with a pitch of 15 \mu \textm . The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42 \mu \textm^2 and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design. |
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| Item Description: | Gesehen am 16.01.2024 |
| Physical Description: | Online Resource |
| ISSN: | 1558-1578 |
| DOI: | 10.1109/TNS.2023.3299333 |